X Architecture: The Year of Production
Silicon
Rita Glover, EDA Today, L.C.
April 2004
The X Architecture is said to reduce the total
wiring on a chip by more than 20 percent and reduce vias by more
than 30 percent, thus improving the performance, power, and cost of
the chip. In October 2003, Toshiba announced that it has
produced the first functional silicon at 90nm using the X
architecture, the first production-worthy approach to diagonal
routing. In December 2003, UMC announced its readiness to
accept X-Architecture designs for 180nm, 150nm, and 130nm processes.
Figure 1: The
shortest route between two points is often on the diagonal.
Now, the X Initiative, a 39-member semiconductor
supply chain consortium formed to accelerate the development of the
X Architecture, sees 2004 as "the year of production silicon."
While it's still early in its adoption cycle, we decided to ask some
of the forerunners for their views on the X Architecture.
Chris Rowen, president and CEO of Tensilica, and Raul Camposano,
senior vice president and chief technical officer of Synopsys,
responded to our questions.
Question: Is the X-architecture
applicable to every design?
Rowen: X Architecture is focused
on improving the interconnect in automatically placed-and-routed
designs. The sweet spot is deep-submicron designs, where
interconnect area, delay, and cost are significant issues.
That's not every design, but it represents a large and growing
fraction of high-volume and high-value system-on-chip designs at
130nm and below.
Camposano: While X-architecture
offers some advantages in low-utilization designs, it is not
applicable to every design. Toshiba has reported 14 percent
wire length reduction and 27 percent via reduction for a very small
chip (300K gates and five metal layers). Theoretically, the
maximum reduction for two-terminal nets is 41 percent, and about 10
percent for multi-terminal nets for planar graphs. For real
designs with high utilization of silicon resources, Synopsys has
found that while the X-architecture offers a small advantage in wire
length (less than 10 percent), it increases vias and shows less
routability.
Another factor that works against the X-architecture
is the increased need for RET for layers in sub-wavelength
lithography. For example, double exposure has been used to
improve the deep-sub-wavelength imaging. In other words, two
complementary exposures are needed, one for vertical lines and the
other for horizontal lines. This becomes tricky when printed
lines include other orientations (for example, 45 and 135 degree
lines). As feature sizes decrease, X can be done only in the
upper layers.
Question: What are the
implications in terms of the design flow? What changes, if
any, will need to be made?
Rowen: The X Initiative members
are systematically identifying and addressing the issues at each
stage along the flow, from logic design and synthesis through to
maskmaking and fabrication. Tensilica's particular focus is on
SOC architecture and logic implementation. In these front-end
stages, few methodological changes are necessary. We believe
that X-aware synthesis and X-aware place-and-route (and perhaps
X-tuned cell libraries) are all that need to be formally evolved.
On the other hand, X appears to open up some
significant new opportunities in SOC architecture. X reduces
wiring cost and delay, so interconnect-intensive architectures are
favored. X will help to accelerate the rise of
multiple-processor SOCs, and will favor high-bandwidth processors
that can take advantage of increased processor-to-processor and
processor-memory bandwidths. We have been working with other X
Initiative members and are quite happy with the performance and cost
impact on configurable processors.
Camposano: Many changes in the
design flow are necessary to support the X-architecture. In
the place and route flow, placement wire length minimization and
congestion estimation enhancement need to assign nets to three sets
in order to minimize wire length, to improve timing performance, and
to reduce congestion/wire length. The three sets are:
These layer assignments need to be honored by the
global router. Steiner tree algorithms need to handle
octilinear trees, and the global router and detailed router need to
handle 45 degrees. Optimizations such as buffer insertion need
to allow 45-degree routing patterns. Extraction also needs to
handle 45 degrees.
Question: Do you perceive any
impact of the X-architecture on the semiconductor IP business?
If so, what?
Rowen: I expect only a
second-order effect on the semiconductor IP business. It will
fall into two areas:
- X helps to close the gap between automatic place-and-route and
custom design, so synthesizable IP in general, and
automatically-generated IP in particular, will be relatively more
attractive.
- As I previously noted, reducing the relative cost of wires
compared to gates encourages more communication-centric
architectures with more distributed intelligence, which will tend
to drive interconnect-rich multiple-processor SOC designs.
Camposano: IP designs are likely
to have very high utilization, so we don't expect the X-architecture
to have a high impact on IP.
Question: What issues does the
X-architecture bring up in terms of manufacturing the chip?
Camposano: Manufacturability is
a significant weakness of the X-architecture at smaller technology
nodes. As already mentioned, 45-degree lines are troublesome
for RET in deep-subwavelength imaging. Some work is being done
to try to address these issues at 130nm and 90nm, but it becomes
more difficult to do 45 degrees at more advanced technology nodes.
One additional point to think about is what happens to the size of
the database and the write time of the masks when the number of data
points needed to capture the 45 degree lines grows.
Rowen: The X architecture
implies a modest additional characterization of the end-to-end
manufacturing flow, especially around lithography, but I don't
anticipate any significant manufacturing changes. On the other
hand, the X architecture does tend to improve routing
characteristics -- especially decreasing the number of vias relative
to Manhattan routing -- which will tend to improve yield, especially
for chip with a large number of routing layers.
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